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(**************************************************************************
$RCSfile: Hardware.mod $
Description: Definitions for Amiga hardware and custom chips
Created by: fjc (Frank Copeland)
$Revision: 3.8 $
$Author: fjc $
$Date: 1995/06/04 23:13:14 $
Includes Release 40.15
(C) Copyright 1985-1993 Commodore-Amiga, Inc.
All Rights Reserved
Oberon-A interface Copyright © 1994-1995, Frank Copeland.
This file is part of the Oberon-A Interface.
See Oberon-A.doc for conditions of use and distribution.
***************************************************************************)
<* STANDARD- *>
MODULE [2] Hardware;
IMPORT SYS := SYSTEM, e := Exec, s := Sets;
(*
** $VER: adkbits.h 39.1 (18.9.92)
**
** bit definitions for adkcon register
*)
CONST
adkSet * = 15; (* standard set/clear bit *)
preComp1 * = 14; (* two bits of precompensation *)
preComp0 * = 13;
mfmPrec * = 12; (* use mfm style precompensation *)
uartBrk * = 11; (* force uart output to zero *)
wordSync * = 10; (* enable DSKSYNC register matching *)
msbSync * = 9; (* (Apple GCR Only) sync on MSB for reading *)
fast * = 8; (* 1 -> 2 us/bit (mfm), 2 -> 4 us/bit (gcr) *)
use3pn * = 7; (* use aud chan 3 to modulate period of ?? *)
use2p3 * = 6; (* use aud chan 2 to modulate period of 3 *)
use1p2 * = 5; (* use aud chan 1 to modulate period of 2 *)
use0p1 * = 4; (* use aud chan 0 to modulate period of 1 *)
use3vn * = 3; (* use aud chan 3 to modulate volume of ?? *)
use2v3 * = 2; (* use aud chan 2 to modulate volume of 3 *)
use1v2 * = 1; (* use aud chan 1 to modulate volume of 2 *)
use0v1 * = 0; (* use aud chan 0 to modulate volume of 1 *)
pre000ns * = {}; (* 000 ns of precomp *)
pre140ns * = { preComp0 }; (* 140 ns of precomp *)
pre280ns * = { preComp1 }; (* 280 ns of precomp *)
pre560ns * = { preComp0, preComp1 }; (* 560 ns of precomp *)
(*
** $VER: blit.h 39.1 (18.9.92)
**
** Defines for direct hardware use of the blitter.
*)
CONST
hSizeBits* = 6;
vSizeBits* = 16-hSizeBits;
hSizeMask* = 3FH; (* 2^6 -- 1 *)
vSizeMask* = 3FFH; (* 2^10 - 1 *)
(* all agnii support horizontal blit of at least 1024 bits (128 bytes) wide *)
(* some agnii support horizontal blit of up to 32768 bits (4096 bytes) wide *)
(* #ifndef NO_BIG_BLITS *)
minBytesPerRow * = 128;
maxBytesPerRow * = 4096;
(* #else *)
(* maxBytesPerRow * = 128; *)
(* #endif *)
(* definitions for blitter control register 0 *)
abc * = 7;
abnc * = 6;
anbc * = 5;
anbnc * = 4;
nabc * = 3;
nabnc * = 2;
nanbc * = 1;
nanbnc* = 0;
(* some commonly used operations *)
aORb * = { abc, anbc, nabc, abnc, anbnc, nabnc };
aORc * = { abc, nabc, abnc, anbc, nanbc, anbnc };
aXORc * = { nabc, abnc, nanbc, anbnc };
aTOd * = { abc, anbc, abnc, anbnc };
dest * = 8;
srcC * = 9;
srcB * = 10;
srcA * = 11;
ash1 * = 12;
ash2 * = 13;
ash4 * = 14;
ash8 * = 15;
desc * = 1; (* blitter descend direction *)
aShiftShift * = 12; (* bits to right align ashift value *)
bShiftShift * = 12; (* bits to right align bshift value *)
(* definations for blitter control register 1 *)
lineMode * = 0;
fillOr * = 3;
fillXor * = 4;
fillCarryIn * = 2;
oneDot * = 1; (* one dot per horizontal line *)
ovFlag * = 5;
signFlag * = 6;
blitReverse * = 1;
sud * = {fillXor};
sul * = {fillOr};
aul * = {fillCarryIn};
octant8 * = sul+sud;
octant7 * = aul;
octant6 * = aul+sul;
octant5 * = aul+sul+sud;
octant4 * = aul+sud;
octant3 * = sul;
octant2 * = {};
octant1 * = sud;
(* stuff for blit qeuer *)
TYPE
BltnodePtr* = POINTER TO Bltnode;
Bltnode* = RECORD
n * : BltnodePtr;
function* : e.PROC;
stat * : CHAR;
blitsize* : INTEGER;
beamsync* : INTEGER;
cleanup * : e.PROC;
END; (* Bltnode *)
CONST
(* defined bits for bltstat *)
cleanup* = 40H;
cleanme* = cleanup;
(*
** $VER: cia.h 39.1 (18.9.92)
**
** registers and bits in the Complex Interface Adapter (CIA) chip
*)
(*
* ciaa is on an ODD address (e.g. the low byte) -- $bfe001
* ciab is on an EVEN address (e.g. the high byte) -- $bfd000
*
* do this to get the definitions:
* extern struct CIA ciaa, ciab;
*)
TYPE
Pad = ARRAY 254 OF SHORTINT;
CIAPtr* = POINTER TO CIA;
CIA* = RECORD
pra * : s.SET8; pad0 * : Pad;
prb * : s.SET8; pad1 * : Pad;
ddra * : s.SET8; pad2 * : Pad;
ddrb * : s.SET8; pad3 * : Pad;
talo * : SHORTINT; pad4 * : Pad;
tahi * : SHORTINT; pad5 * : Pad;
tblo * : SHORTINT; pad6 * : Pad;
tbhi * : SHORTINT; pad7 * : Pad;
todlow* : SHORTINT; pad8 * : Pad;
todmid* : SHORTINT; pad9 * : Pad;
todhi * : SHORTINT; pad10* : Pad;
unusedreg* : s.SET8; pad11* : Pad;
sdr * : SHORTINT; pad12* : Pad;
icr * : s.SET8; pad13* : Pad;
cra * : s.SET8; pad14* : Pad;
crb * : s.SET8;
END; (* CIA *)
CONST
(* interrupt control register bit numbers *)
ta * = 0;
tb * = 1;
alrm * = 2;
sp * = 3;
flg * = 4;
ir * = 7;
setClr * = 7;
(* control register A bit numbers *)
craStart * = 0;
craPbon * = 1;
craOutmode* = 2;
craRunmode* = 3;
craLoad * = 4;
craInmode * = 5;
craSpmode * = 6;
craTodin * = 7;
(* control register B bit numbers *)
crbStart * = 0;
crbPbon * = 1;
crbOutmode* = 2;
crbRunmode* = 3;
crbLoad * = 4;
crbInmode0* = 5;
crbInmode1* = 6;
crbAlarm * = 7;
(*
* Port definitions -- what each bit in a cia peripheral register is tied to
*)
(* ciaa port A (0BFE001H) *)
gamePort1 * = 7; (* gameport 1, pin 6 (fire button) *)
gamePort0 * = 6; (* gameport 0, pin 6 (fire button) *)
dskRdy * = 5; (* disk ready *)
dskTrack0 * = 4; (* disk on track 00 *)
dskProt * = 3; (* disk write protect *)
dskChange * = 2; (* disk change *)
led * = 1; (* led light control (0==>bright) *)
overlay * = 0; (* memory overlay bit *)
(* ciaa port B (0BFE101H) -- parallel port *)
(* ciab port A (0BFD000H) -- serial and printer control *)
comDTR * = 7; (* serial Data Terminal Ready *)
comRTS * = 6; (* serial Request to Send *)
comCD * = 5; (* serial Carrier Detect *)
comCTS * = 4; (* serial Clear to Send *)
comDSR * = 3; (* serial Data Set Ready *)
prtrSel * = 2; (* printer SELECT *)
prtrPOut * = 1; (* printer paper out *)
prtrBusy * = 0; (* printer busy *)
(* ciab port B (0BFD100H) -- disk control *)
dskMotor * = 7; (* disk motorr *)
dskSel3 * = 6; (* disk select unit 3 *)
dskSel2 * = 5; (* disk select unit 2 *)
dskSel1 * = 4; (* disk select unit 1 *)
dskSel0 * = 3; (* disk select unit 0 *)
dskSide * = 2; (* disk side select *)
dskDirec * = 1; (* disk direction of seek *)
dskStep * = 0; (* disk step heads *)
(* cia addresses, initialised to point to correct addresses *)
VAR
ciaa* : CIAPtr;
ciab* : CIAPtr;
(*
** $VER: custom.h 39.1 (18.9.92)
**
** Offsets of Amiga custom chip registers
*)
(*
* do this to get base of custom registers:
* extern struct Custom custom;
*)
TYPE
Coord * = RECORD v*,h*: SHORTINT END;
SerialInfo * = RECORD flags * : s.SET8; data * : CHAR END;
DiskInfo * = RECORD flags * : s.SET8; data * : SYS.BYTE END;
AudChannelPtr* = POINTER TO AudChannel;
AudChannel* = RECORD
ptr* : e.APTR; (* ptr to start of waveform data *)
len* : e.UWORD; (* length of waveform in words *)
per* : e.UWORD; (* sample period *)
vol* : e.UWORD; (* volume *)
dat* : e.UWORD; (* sample pair *)
pad* : ARRAY 2 OF e.UWORD; (* unused *)
END; (* AudChannel *)
AudChannels* = ARRAY 4 OF AudChannel;
SpriteDefPtr* = POINTER TO SpriteDef;
SpriteDef* = RECORD
pos * : e.UWORD;
ctl * : RECORD
ev * : SYS.BYTE;
flags * : s.SET8;
END;
data * : LONGINT;
END; (* SpriteDef *)
SpriteDefs * = ARRAY 8 OF SpriteDef;
CustomPtr* = POINTER TO Custom;
Custom* = RECORD
bltddat * : e.UWORD;
dmaconr * : s.SET16;
vposr * : e.UWORD;
vhposr * : e.UWORD;
dskdatr * : e.UWORD;
joy0dat * : Coord;
joy1dat * : Coord;
clxdat * : s.SET16;
adkconr * : s.SET16;
pot0dat * : Coord;
pot1dat * : Coord;
potinp * : s.SET16;
serdatr * : SerialInfo;
dskbytr * : DiskInfo;
intenar * : s.SET16;
intreqr * : s.SET16;
dskpt * : e.APTR;
dsklen * : e.UWORD;
dskdat * : e.UWORD;
refptr * : e.UWORD;
vposw * : e.UWORD;
vhposw * : e.UWORD;
copcon * : s.SET16;
serdat * : SerialInfo;
serper * : e.UWORD;
potgo * : s.SET16;
joytest * : Coord;
strequ * : e.UWORD;
strvbl * : e.UWORD;
strhor * : e.UWORD;
strlong * : e.UWORD;
bltcon0 * : s.SET16;
bltcon1 * : s.SET16;
bltafwm * : s.SET16;
bltalwm * : s.SET16;
bltcpt * : e.APTR;
bltbpt * : e.APTR;
bltapt * : e.APTR;
bltdpt * : e.APTR;
bltsize * : e.UWORD;
pad2d * : SYS.BYTE;
bltcon0l* : s.SET8; (* low 8 bits of bltcon0, write only *)
bltsizv * : e.UWORD;
bltsizh * : e.UWORD; (* 5e *)
bltcmod * : e.UWORD;
bltbmod * : e.UWORD;
bltamod * : e.UWORD;
bltdmod * : e.UWORD;
pad34 * : ARRAY 4 OF e.UWORD;
bltcdat * : e.UWORD;
bltbdat * : e.UWORD;
bltadat * : e.UWORD;
pad3b * : ARRAY 3 OF e.UWORD;
deniseid* : e.UWORD; (* 7c *)
dsksync * : e.UWORD;
cop1lc * : e.ULONG;
cop2lc * : e.ULONG;
copjmp1 * : e.UWORD;
copjmp2 * : e.UWORD;
copins * : e.UWORD;
diwstrt * : Coord;
diwstop * : Coord;
ddfstrt * : Coord;
ddfstop * : Coord;
dmacon * : s.SET16;
clxcon * : s.SET16;
intena * : s.SET16;
intreq * : s.SET16;
adkcon * : s.SET16;
aud * : AudChannels;
bplpt * : ARRAY 8 OF e.APTR;
bplcon0 * : s.SET16;
bplcon1 * : s.SET16;
bplcon2 * : s.SET16;
bplcon3 * : s.SET16;
bpl1mod * : e.UWORD;
bpl2mod * : e.UWORD;
bplhmod * : e.UWORD;
pad86 * : e.UWORD;
bpldat * : ARRAY 8 OF e.UWORD;
sprpt * : ARRAY 8 OF e.APTR;
spr * : SpriteDefs;
color * : ARRAY 32 OF e.UWORD;
htotal * : e.UWORD;
hsstop * : e.UWORD;
hbstrt * : e.UWORD;
hbstop * : e.UWORD;
vtotal * : e.UWORD;
vsstop * : e.UWORD;
vbstrt * : e.UWORD;
vbstop * : e.UWORD;
sprhstrt* : e.UWORD;
sprhstop* : e.UWORD;
bplhstrt* : e.UWORD;
bplhstop* : e.UWORD;
hhposw * : e.UWORD;
hhposr * : e.UWORD;
beamcon0* : s.SET16;
hsstrt * : e.UWORD;
vsstrt * : e.UWORD;
hcenter * : e.UWORD;
diwhigh * : e.UWORD; (* 1e4 *)
padf3 * : ARRAY 11 OF e.UWORD;
fmode * : e.UWORD;
END; (* Custom *)
CONST
(* defines for beamcon register *)
varVBlank * = 13; (* Variable vertical blank enable *)
loLDis * = 12; (* long line disable *)
cscBlankEn * = 11; (* redirect composite sync *)
varVSync * = 10; (* Variable vertical sync enable *)
varHSync * = 9; (* Variable horizontal sync enable *)
varBeam * = 8; (* variable beam counter enable *)
displayDual * = 7; (* use UHRES pointer and standard pointers *)
displayPAL * = 6; (* set decodes to generate PAL display *)
varCSync * = 5; (* Variable composite sync enable *)
csBlank * = 4; (* Composite blank out to CSY* pin *)
cSyncTrue * = 3; (* composite sync true signal *)
vSyncTrue * = 1; (* vertical sync true *)
hSyncTrue * = 0; (* horizontal sync true *)
(* new defines for bplcon0 *)
useBplCon3 * = 1;
(* new defines for bplcon2 *)
zdCTen * = 10; (* colormapped genlock bit *)
zdBPen * = 11; (* use bitplane as genlock bits *)
zdBPSel0 * = 12; (* three bits to select one *)
zdBPSel1 * = 13; (* of 8 bitplanes in *)
zdBPSel2 * = 14; (* zdBPen genlock mode *)
(* defines for bplcon3 register *)
extBlnkEn * = 0; (* external blank enable *)
extBlkZD * = 1; (* external blank ored into trnsprncy *)
zdClkEn * = 2; (* zd pin outputs a 14mhz clock*)
brdnTran * = 4; (* border is opaque *)
brdnBlnk * = 5; (* border is opaque *)
(* Pointer to custom hardware *)
VAR
custom* : CustomPtr;
(*
** $VER: dmabits.h 39.1 (18.9.92)
**
** include file for defining dma control stuff
*)
CONST
(* write definitions for dmaconw *)
dmaSet * = 15;
aud0 * = 0;
aud1 * = 1;
aud2 * = 2;
aud3 * = 3;
audio * = {aud0, aud1, aud2, aud3}; (* 4 bit mask *)
disk * = 4;
sprite * = 5;
blitter* = 6;
copper * = 7;
raster * = 8;
master * = 9;
blithog* = 10;
all* = {aud0 .. raster}; (* all dma channels *)
bitSet * = {dmaSet};
bitClr * = {};
(* read definitions for dmaconr *)
(* bits 0-8 correspnd to dmaconw definitions *)
bltDone * = 14;
bltNZero * = 13;
(*
** $VER: intbits.h 39.1 (18.9.92)
**
** bits in the interrupt enable (and interrupt request) register
*)
CONST
intSet * = 15; (* Set/Clear control bit. Determines if bits *)
(* written with a 1 get set or cleared. Bits *)
(* written with a zero are allways unchanged *)
intEn * = 14; (* Master interrupt (enable only ) *)
exter * = 13; (* External interrupt *)
dskSync * = 12; (* Disk re-SYNChronized *)
rbf * = 11; (* serial port Receive Buffer Full *)
aud3i * = 10; (* Audio channel 3 block finished *)
aud2i * = 9; (* Audio channel 2 block finished *)
aud1i * = 8; (* Audio channel 1 block finished *)
aud0i * = 7; (* Audio channel 0 block finished *)
blit * = 6; (* Blitter finished *)
vertb * = 5; (* start of Vertical Blank *)
coper * = 4; (* Coprocessor *)
ports * = 3; (* I/O Ports and timers *)
softint * = 2; (* software interrupt request *)
dskblk * = 1; (* Disk Block done *)
tbe * = 0; (* serial port Transmit Buffer Empty *)
<*$LongVars-*>
BEGIN
ciaa := SYS.VAL (CIAPtr, 00BFE001H);
ciab := SYS.VAL (CIAPtr, 00BFD000H);
custom := SYS.VAL (CustomPtr, 00DFF000H);
END Hardware.